ADC_CTRL Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.450s	6.055ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.650s	1.224ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.780s	410.326us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.091m	27.026ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.140s	1.315ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.290s	575.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.780s	410.326us	20	20	100.00
		adc_ctrl_csr_aliasing	6.140s	1.315ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.633m	495.480ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.832m	496.074ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.316m	492.731ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.300m	489.481ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.228m	494.752ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	18.713m	494.389ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.575m	504.252ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	17.382m	481.376ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.460s	5.179ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.721m	45.568ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.162m	131.261ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	29.471m	627.223ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.690s	488.473us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.800s	494.248us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.700s	744.652us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.700s	744.652us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.650s	1.224ms	5	5	100.00
		adc_ctrl_csr_rw	1.780s	410.326us	20	20	100.00
		adc_ctrl_csr_aliasing	6.140s	1.315ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.240s	4.930ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.650s	1.224ms	5	5	100.00
		adc_ctrl_csr_rw	1.780s	410.326us	20	20	100.00
		adc_ctrl_csr_aliasing	6.140s	1.315ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.240s	4.930ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	9.940s	7.861ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.970s	8.254ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.970s	8.254ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.043m	612.016ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			910	920	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.58	98.98	95.69	100.00	100.00	98.18	98.64	91.54

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 9 failures:

Test adc_ctrl_stress_all has 6 failures.

1.adc_ctrl_stress_all.29922622791773597057131248715179678028884125385154999106024097540668978737976
Line 397, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 644462488954 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 644462488954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.adc_ctrl_stress_all.48421121715941387501701056980032118927513789170478622290236244295380883647219
Line 448, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 365950613211 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 365950613211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 3 failures.

15.adc_ctrl_stress_all_with_rand_reset.54926999649553020442506121866952947810195830743443833208966452366816615506218
Line 762, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1170905054745 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 1170905054745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.adc_ctrl_stress_all_with_rand_reset.86401353521293967184271408690898179646063567481643739269046807924969572986199
Line 394, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 416695439154 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 416695439154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 14.adc_ctrl_stress_all_with_rand_reset.25158084363328459057876072056388761694339113283733553689123659215499045578042
    Line 503, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 273329781924 ps: (adc_ctrl_fsm.sv:376) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 273329781924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```