ADC_CTRL Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.960s	5.941ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.470s	1.225ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.990s	506.460us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.693m	47.237ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.400s	845.323us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.270s	518.679us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.990s	506.460us	20	20	100.00
		adc_ctrl_csr_aliasing	4.400s	845.323us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.715m	495.456ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.338m	487.829ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.327m	499.405ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.100m	496.259ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.194m	520.444ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.058m	504.087ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.243m	487.519ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	18.354m	494.620ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.540s	5.044ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.762m	46.402ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.929m	138.480ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.088m	672.535ms	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	1.820s	523.923us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.820s	528.834us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.560s	601.525us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.560s	601.525us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.470s	1.225ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	506.460us	20	20	100.00
		adc_ctrl_csr_aliasing	4.400s	845.323us	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.380s	5.565ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.470s	1.225ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	506.460us	20	20	100.00
		adc_ctrl_csr_aliasing	4.400s	845.323us	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.380s	5.565ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	20.610s	8.185ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.130s	8.523ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.130s	8.523ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.191m	401.523ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			914	920	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	14	87.50
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	98.98	95.69	100.00	100.00	98.18	98.64	91.72

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:
  • Test adc_ctrl_stress_all has 5 failures.

    • 14.adc_ctrl_stress_all.3726403094531409334512687208251163894365140783413760746164137500966041023129
      Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 333219347673 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 333219347673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.adc_ctrl_stress_all.20259898887326633472727845441411960982650593730117012338888252582354299102376
      Line 378, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 490817931889 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 490817931889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 2.adc_ctrl_filters_both.6633372667642888922343093576614222358243707234217065451569606529332691431849
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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