ADC_CTRL Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.710s	5.983ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.850s	1.257ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.040s	485.617us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.890m	52.210ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.600s	838.724us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.260s	572.602us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.040s	485.617us	20	20	100.00
		adc_ctrl_csr_aliasing	4.600s	838.724us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.079m	489.260ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.896m	482.751ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.411m	495.544ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.451m	493.421ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.236m	519.964ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.505m	492.394ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.475m	495.735ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	16.996m	493.097ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.070s	5.375ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.859m	44.891ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.161m	129.018ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	24.640m	515.410ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.950s	497.137us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.900s	514.492us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.080s	610.027us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.080s	610.027us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.850s	1.257ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	485.617us	20	20	100.00
		adc_ctrl_csr_aliasing	4.600s	838.724us	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.570s	5.176ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.850s	1.257ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	485.617us	20	20	100.00
		adc_ctrl_csr_aliasing	4.600s	838.724us	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.570s	5.176ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	18.660s	7.794ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.560s	8.395ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.560s	8.395ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.290m	524.232ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			912	920	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.47	98.98	95.69	100.00	100.00	98.18	98.64	90.82

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 7 failures:

Test adc_ctrl_stress_all_with_rand_reset has 3 failures.

11.adc_ctrl_stress_all_with_rand_reset.15515575427969038294428805711283597793226493835729237876679358577086684432729
Line 377, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 398570404273 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 398570404273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.adc_ctrl_stress_all_with_rand_reset.30060778805282425084386015547114504092047337837161668468878641761544168710293
Line 368, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 183744102019 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 183744102019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all has 4 failures.

14.adc_ctrl_stress_all.97650796911788556936646482350558314996509165683443959167612902243251993600583
Line 397, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 662969596303 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 662969596303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.adc_ctrl_stress_all.3687543010588051738089711316496271484749138038800646696993660873438909439240
Line 361, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 328287067789 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 328287067789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:135) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.adc_ctrl_stress_all_with_rand_reset.7282463602165608656289280954108140337010951656132604334154721150663693557611
    Line 462, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82963127389 ps: (adc_ctrl_scoreboard.sv:135) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 82963127389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```