ADC_CTRL Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.050s	5.768ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.510s	1.160ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.910s	516.488us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.673m	53.122ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.070s	770.810us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.290s	613.800us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.910s	516.488us	20	20	100.00
		adc_ctrl_csr_aliasing	3.070s	770.810us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.910m	500.942ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.675m	487.886ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.389m	495.874ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.220m	490.587ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.331m	501.674ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.609m	499.355ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.482m	496.759ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.253m	491.680ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.880s	5.438ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.838m	45.805ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.924m	144.724ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.020m	601.422ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.850s	493.845us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	519.995us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.180s	546.407us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.180s	546.407us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.510s	1.160ms	5	5	100.00
		adc_ctrl_csr_rw	1.910s	516.488us	20	20	100.00
		adc_ctrl_csr_aliasing	3.070s	770.810us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.830s	4.493ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.510s	1.160ms	5	5	100.00
		adc_ctrl_csr_rw	1.910s	516.488us	20	20	100.00
		adc_ctrl_csr_aliasing	3.070s	770.810us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.830s	4.493ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	8.800s	3.997ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.080s	8.122ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.080s	8.122ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	28.918m	888.035ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			914	920	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.63	98.98	95.69	100.00	100.00	98.18	98.64	91.92

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 6 failures:

Test adc_ctrl_stress_all has 4 failures.

0.adc_ctrl_stress_all.32230393732266613824567137430929520333914424675586189647371049540146163614226
Line 373, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 329633877381 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 329633877381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.adc_ctrl_stress_all.75464526986366528509799042739667479750636931692146220939017805493521120819683
Line 441, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 516385205982 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 516385205982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

25.adc_ctrl_stress_all_with_rand_reset.12226913051427680734947553538688972643721019850771960283097411174317237599637
Line 476, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 391713390496 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 391713390496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.adc_ctrl_stress_all_with_rand_reset.112926607351005667239434724869043767584500723078949911522623500928376040981242
Line 420, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 241404383165 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 241404383165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---