ADC_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.900s	5.923ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.720s	1.329ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.960s	515.206us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.895m	50.097ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.140s	1.206ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.940s	388.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.960s	515.206us	20	20	100.00
		adc_ctrl_csr_aliasing	5.140s	1.206ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.107m	491.215ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.887m	497.866ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.070m	491.242ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.807m	497.778ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.657m	542.111ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.435m	615.716ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.734m	530.747ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.249m	512.611ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.650s	5.302ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.802m	45.019ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.524m	136.740ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	34.764m	864.713ms	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	1.960s	528.260us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.010s	526.490us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.060s	620.279us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.060s	620.279us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.720s	1.329ms	5	5	100.00
		adc_ctrl_csr_rw	1.960s	515.206us	20	20	100.00
		adc_ctrl_csr_aliasing	5.140s	1.206ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.720s	5.292ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.720s	1.329ms	5	5	100.00
		adc_ctrl_csr_rw	1.960s	515.206us	20	20	100.00
		adc_ctrl_csr_aliasing	5.140s	1.206ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.720s	5.292ms	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	tl_intg_err	adc_ctrl_sec_cm	19.980s	8.201ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.460s	8.649ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.460s	8.649ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.404m	356.834ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			913	920	99.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.10	96.68	100.00	100.00	98.88	98.33	91.24

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:409) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 7 failures:

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

7.adc_ctrl_stress_all_with_rand_reset.3384344336958103834540053129037101862196487050312286798872427993421421419894
Line 608, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 410543745572 ps: (adc_ctrl_scoreboard.sv:409) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 410543745572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.adc_ctrl_stress_all_with_rand_reset.35988715850736401142087127803770585373634590924534495845120004491639919842588
Line 525, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 615461223014 ps: (adc_ctrl_scoreboard.sv:409) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 615461223014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 5 failures.

33.adc_ctrl_stress_all.95540297375750229318194294022213307043460996185838674001428130484130149511763
Line 378, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 496719154080 ps: (adc_ctrl_scoreboard.sv:409) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 496719154080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.adc_ctrl_stress_all.11754375595945876029885243147070764150686923101801310833272026595799951207560
Line 405, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 593121223766 ps: (adc_ctrl_scoreboard.sv:409) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 593121223766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.