ADC_CTRL Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.590s	5.883ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.570s	828.609us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.110s	515.016us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.019m	52.326ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.870s	1.131ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.470s	675.978us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.110s	515.016us	20	20	100.00
		adc_ctrl_csr_aliasing	5.870s	1.131ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.905m	492.307ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.491m	500.947ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.582m	485.855ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.603m	483.157ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.571m	646.337ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.244m	607.707ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	24.270m	564.802ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.292m	543.763ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.350s	4.594ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.654m	45.673ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.462m	142.235ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	18.240m	302.334ms	42	50	84.00
V2	alert_test	adc_ctrl_alert_test	1.890s	531.368us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	516.116us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.640s	516.421us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.640s	516.421us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.570s	828.609us	5	5	100.00
		adc_ctrl_csr_rw	2.110s	515.016us	20	20	100.00
		adc_ctrl_csr_aliasing	5.870s	1.131ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.900s	4.566ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.570s	828.609us	5	5	100.00
		adc_ctrl_csr_rw	2.110s	515.016us	20	20	100.00
		adc_ctrl_csr_aliasing	5.870s	1.131ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.900s	4.566ms	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	tl_intg_err	adc_ctrl_sec_cm	20.790s	7.910ms	5	5	100.00
		adc_ctrl_tl_intg_err	25.800s	8.862ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	25.800s	8.862ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	19.058m	1.010s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			912	920	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	96.63	100.00	100.00	98.76	98.33	91.29

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:404) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:
- Test adc_ctrl_stress_all has 6 failures.
  - 3.adc_ctrl_stress_all.53779257340637909197153484033707975972289813862820544577130569775555569457427
    Line 485, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 545164669202 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 545164669202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.adc_ctrl_stress_all.17292871228439836422629412123852788681733858276727954048881916393097063064897
    Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 326283358992 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 326283358992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*])

has 2 failures:

Test adc_ctrl_stress_all has 2 failures.

15.adc_ctrl_stress_all.75686384565989241475483888053576196157076376842198905513393140335257342250422
Line 381, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 270512138527 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 270512138527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.adc_ctrl_stress_all.56872289738891150556462342515798508302182145535312151893382478428895692864261
Line 345, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 190141081317 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 190141081317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---