ADC_CTRL Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.710s	6.090ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.740s	1.190ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.030s	567.516us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.401m	52.029ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.540s	868.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	535.990us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.030s	567.516us	20	20	100.00
		adc_ctrl_csr_aliasing	4.540s	868.583us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.507m	495.553ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.180m	494.126ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.259m	484.702ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.829m	500.286ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.741m	619.507ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.340m	606.041ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.148m	556.941ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.657m	569.131ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.990s	5.167ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.815m	43.961ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.184m	144.435ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	31.872m	487.317ms	43	50	86.00
V2	alert_test	adc_ctrl_alert_test	1.770s	499.142us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.820s	436.241us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.650s	475.231us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.650s	475.231us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.740s	1.190ms	5	5	100.00
		adc_ctrl_csr_rw	2.030s	567.516us	20	20	100.00
		adc_ctrl_csr_aliasing	4.540s	868.583us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.030s	4.903ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.740s	1.190ms	5	5	100.00
		adc_ctrl_csr_rw	2.030s	567.516us	20	20	100.00
		adc_ctrl_csr_aliasing	4.540s	868.583us	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.030s	4.903ms	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	tl_intg_err	adc_ctrl_sec_cm	17.700s	7.719ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.000s	8.191ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.000s	8.191ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.400m	273.418ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			910	920	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	14	87.50
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:404) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:

Test adc_ctrl_stress_all has 4 failures.

5.adc_ctrl_stress_all.89749059293851935379913102979265652117902822865094008858035360552266073401323
Line 401, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1919301017069 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 1919301017069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.adc_ctrl_stress_all.36980291479010316938548741412053892982313255743985234981912905374708861538185
Line 373, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 329084171078 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 329084171078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

35.adc_ctrl_stress_all_with_rand_reset.68420117224784032722709494025380944484656873545511373401737377388406702624962
Line 478, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 412253535365 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 412253535365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.adc_ctrl_stress_all_with_rand_reset.78349789236606932390658166547926213443620975390643431386390206053211535473636
Line 376, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 216730984753 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 216730984753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 3 failures:
- Test adc_ctrl_stress_all has 3 failures.
  - 0.adc_ctrl_stress_all.69647119329582415392349049595708062754390991092316802708230837298518532457044
    Line 346, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 174134470726 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 174134470726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.adc_ctrl_stress_all.73714645556910564152029461801924808357558468780754327353117557381898170095095
    Line 345, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 161502679532 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 161502679532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 17.adc_ctrl_filters_both.32266879888853924049802551344038991874456597458744098397170400184382507215878
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```