ADC_CTRL Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.750s	6.056ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.710s	1.228ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.080s	508.058us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.038m	51.818ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.320s	979.342us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.070s	519.770us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.080s	508.058us	20	20	100.00
		adc_ctrl_csr_aliasing	5.320s	979.342us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	13.463m	336.454ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.187m	489.867ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.192m	493.231ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.128m	488.906ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.167m	560.544ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.661m	600.952ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.728m	504.749ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	22.626m	558.958ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.930s	5.297ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.695m	43.820ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.404m	136.204ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	43.753m	1.155s	42	50	84.00
V2	alert_test	adc_ctrl_alert_test	1.780s	533.635us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	515.388us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.460s	548.511us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.460s	548.511us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.710s	1.228ms	5	5	100.00
		adc_ctrl_csr_rw	2.080s	508.058us	20	20	100.00
		adc_ctrl_csr_aliasing	5.320s	979.342us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.940s	4.655ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.710s	1.228ms	5	5	100.00
		adc_ctrl_csr_rw	2.080s	508.058us	20	20	100.00
		adc_ctrl_csr_aliasing	5.320s	979.342us	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.940s	4.655ms	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	tl_intg_err	adc_ctrl_sec_cm	10.770s	4.181ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.040s	8.659ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.040s	8.659ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	18.048m	594.102ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			911	920	99.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.07	96.67	100.00	100.00	98.83	98.33	90.92

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:404) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:
- Test adc_ctrl_stress_all has 5 failures.
  - 2.adc_ctrl_stress_all.19641284479900119697439580187680300969580354186157901540176695937959722591858
    Line 448, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 375657695394 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 375657695394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.adc_ctrl_stress_all.108785987913942444465917855790668443907030892577537366280699132978610560153191
    Line 374, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 345351378319 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 345351378319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*])

has 4 failures:

Test adc_ctrl_stress_all has 3 failures.

28.adc_ctrl_stress_all.49979629043017270262221261283081277914025276781219152305334868051639942301536
Line 344, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 161540768013 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 161540768013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.adc_ctrl_stress_all.39096078322873476075112455075680477144873945481929641121267668386555980497165
Line 344, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 160851115271 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 160851115271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

32.adc_ctrl_stress_all_with_rand_reset.115776049082957315281451543484459900813636078025788717864154223043364994849459
Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 203382035501 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 203382035501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---