ADC_CTRL Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.620s	5.890ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.020s	940.325us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.180s	473.957us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.970m	50.911ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.830s	1.182ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.370s	667.488us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.180s	473.957us	20	20	100.00
		adc_ctrl_csr_aliasing	4.830s	1.182ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.626m	487.081ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.494m	488.815ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.272m	491.900ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.803m	502.035ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.143m	582.249ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.248m	609.437ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.240m	566.437ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.317m	562.332ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.830s	5.384ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.813m	43.556ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.742m	134.185ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	34.427m	1.754s	41	50	82.00
V2	alert_test	adc_ctrl_alert_test	1.850s	499.694us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.890s	521.618us	49	50	98.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.730s	554.664us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.730s	554.664us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.020s	940.325us	5	5	100.00
		adc_ctrl_csr_rw	2.180s	473.957us	20	20	100.00
		adc_ctrl_csr_aliasing	4.830s	1.182ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.700s	4.672ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.020s	940.325us	5	5	100.00
		adc_ctrl_csr_rw	2.180s	473.957us	20	20	100.00
		adc_ctrl_csr_aliasing	4.830s	1.182ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.700s	4.672ms	20	20	100.00
V2		TOTAL			728	740	98.38
V2S	tl_intg_err	adc_ctrl_sec_cm	10.520s	4.137ms	5	5	100.00
		adc_ctrl_tl_intg_err	16.740s	8.798ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	16.740s	8.798ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.006m	151.027ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			903	920	98.15

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.17

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:404) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 7 failures:

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

5.adc_ctrl_stress_all_with_rand_reset.68265578774997030263893900626082898503790837546419072749505680012528905431859
Line 455, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 315206397869 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 315206397869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.adc_ctrl_stress_all_with_rand_reset.73882200347067872111949254427599411212738936014296166789847710404951300289133
Line 462, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 163902217573 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 163902217573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 5 failures.

22.adc_ctrl_stress_all.81833117531770176470284744871110907770697307916475925167398264322849434631102
Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 348133147931 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 348133147931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.adc_ctrl_stress_all.28587388117594846200733558830243202486539982883853786890309744999244657761074
Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 354694725621 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 354694725621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 6 failures:

Test adc_ctrl_stress_all has 4 failures.

16.adc_ctrl_stress_all.77412756482318893026185869434788450062936694585819391034143998440023324527466
Line 382, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 537104845084 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 537104845084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.adc_ctrl_stress_all.46896438919042815165602526030645891699931316142929828060529602072510990242222
Line 355, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 173285690209 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 173285690209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

17.adc_ctrl_stress_all_with_rand_reset.71906716538460937230449698635761898796762067468957965363128709497169112340091
Line 417, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 339597171602 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 339597171602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.adc_ctrl_stress_all_with_rand_reset.93911947891156371541000982907934347659322163053204240433472975834106131597
Line 362, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 175387706372 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 175387706372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 2.adc_ctrl_filters_both.21111275176607946903933803008564032345955373109220897129953339073050534626209
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.adc_ctrl_filters_both.61068136277521272156174027122208762059210064594556604302758205052875462125120
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.adc_ctrl_stress_all_with_rand_reset.64963096805777570617459741548243877591740577486907211418194227023674819094587
    Line 498, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 97100325158 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 97100325158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test adc_ctrl_intr_test has 1 failures.

34.adc_ctrl_intr_test.90732122771684715210038664950446945824224060995830375131010642354088974367239
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest/run.log

  [make]: simulate
  cd /workspace/34.adc_ctrl_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975059463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.975059463
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Mar 17 12:59 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255