ADC_CTRL Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.240s	5.913ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.050s	1.410ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.250s	554.577us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	3.641m	52.954ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.870s	1.269ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.400s	548.431us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.250s	554.577us	20	20	100.00
		adc_ctrl_csr_aliasing	5.870s	1.269ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.339m	491.525ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.801m	492.609ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.827m	494.762ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.672m	505.673ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.062m	560.891ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	26.866m	623.330ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	24.537m	583.724ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	15.595m	368.215ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.090s	5.668ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.883m	45.846ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.488m	141.669ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	2.322h	3.624s	43	50	86.00
V2	alert_test	adc_ctrl_alert_test	1.800s	529.929us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	472.890us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.710s	524.310us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.710s	524.310us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.050s	1.410ms	5	5	100.00
		adc_ctrl_csr_rw	2.250s	554.577us	20	20	100.00
		adc_ctrl_csr_aliasing	5.870s	1.269ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.620s	2.668ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.050s	1.410ms	5	5	100.00
		adc_ctrl_csr_rw	2.250s	554.577us	20	20	100.00
		adc_ctrl_csr_aliasing	5.870s	1.269ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.620s	2.668ms	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	tl_intg_err	adc_ctrl_sec_cm	6.080s	8.436ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.880s	8.420ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.880s	8.420ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.566m	619.315ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			909	920	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	14	87.50
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.12

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:404) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:

Test adc_ctrl_stress_all has 4 failures.

1.adc_ctrl_stress_all.71090551635623466420385764563832300985245556658048559366932308408572652607417
Line 387, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1170616147921 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 1170616147921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.adc_ctrl_stress_all.24504282142686142544590337399516264818495251120659071846129052505192035855239
Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 326471769701 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 326471769701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

20.adc_ctrl_stress_all_with_rand_reset.64353279187502694633628612189517932219501929942506865130175872326828183384714
Line 467, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 503723580484 ps: (adc_ctrl_scoreboard.sv:404) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 503723580484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 4 failures:

Test adc_ctrl_stress_all has 3 failures.

2.adc_ctrl_stress_all.12813171362196842370475782407157199143919225060589117720504547018304600416404
Line 365, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 364279602444 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 364279602444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.adc_ctrl_stress_all.4682384510544138143201885888219691575351078996119418664028976060701815998353
Line 345, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 167301122076 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 167301122076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

4.adc_ctrl_stress_all_with_rand_reset.2258765064959078040844092592657685132217909133431165012597153749873286181344
Line 370, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 167228042385 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 167228042385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 17.adc_ctrl_filters_both.3388393742037556413814488759047303009840317770167149377292590603805514618636
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.adc_ctrl_filters_both.78374287308907688315741068268966182177421203561111087808037379624946004202996
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```