ADC_CTRL Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.960s	5.662ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.170s	1.493ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.200s	559.163us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.558m	49.972ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.870s	974.517us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.360s	552.570us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.200s	559.163us	20	20	100.00
		adc_ctrl_csr_aliasing	3.870s	974.517us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.180m	493.471ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.770m	508.196ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.134m	495.254ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.621m	490.940ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.191m	541.730ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.103m	600.296ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.717m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.353m	513.022ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.720s	5.268ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.722m	42.780ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.136m	133.778ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.712m	720.217ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.730s	525.866us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	504.326us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.720s	552.475us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.720s	552.475us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.170s	1.493ms	5	5	100.00
		adc_ctrl_csr_rw	2.200s	559.163us	20	20	100.00
		adc_ctrl_csr_aliasing	3.870s	974.517us	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.280s	4.633ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.170s	1.493ms	5	5	100.00
		adc_ctrl_csr_rw	2.200s	559.163us	20	20	100.00
		adc_ctrl_csr_aliasing	3.870s	974.517us	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.280s	4.633ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	11.620s	4.400ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.760s	8.680ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.760s	8.680ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.325m	1.120s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.07	96.62	100.00	100.00	98.83	98.33	91.09

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 0.adc_ctrl_filters_both.97429301308172298039185859641817987491466297411328150452115091573322580841937
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.adc_ctrl_filters_both.55729795536511967370514245604937010071584031061842279395814603763893624793877
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.20_03.25.21
• 2024.03.18_04.23.28
• 2024.03.14_23.57.48
• 2024.03.13_03.54.33
• 2024.03.11_03.07.20
• 2024.03.08_04.59.35