ADC_CTRL Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.060s	6.120ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.690s	1.247ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.250s	538.887us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.161m	52.653ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.190s	777.562us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.360s	661.265us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.250s	538.887us	20	20	100.00
		adc_ctrl_csr_aliasing	4.190s	777.562us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.842m	498.451ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.863m	485.218ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.105m	498.574ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.696m	490.710ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.798m	600.905ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.959m	601.874ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.400m	580.932ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.569m	498.902ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.240s	5.149ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.614m	42.262ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.036m	131.409ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	33.809m	375.991ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.920s	527.173us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.780s	445.759us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.930s	553.798us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.930s	553.798us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.690s	1.247ms	5	5	100.00
		adc_ctrl_csr_rw	2.250s	538.887us	20	20	100.00
		adc_ctrl_csr_aliasing	4.190s	777.562us	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.690s	4.736ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.690s	1.247ms	5	5	100.00
		adc_ctrl_csr_rw	2.250s	538.887us	20	20	100.00
		adc_ctrl_csr_aliasing	4.190s	777.562us	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.690s	4.736ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.140s	8.125ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.220s	8.155ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.220s	8.155ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.738m	546.120ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.07	96.67	100.00	100.00	98.83	98.33	91.09

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 27.adc_ctrl_filters_both.32341459429883146595275663569978865054677262137911476834309585261337060775966
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.22_04.20.35
• 2024.03.20_03.25.21
• 2024.03.18_04.23.28
• 2024.03.14_23.57.48
• 2024.03.13_03.54.33
• 2024.03.11_03.07.20