ADC_CTRL Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.860s	5.679ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.200s	974.506us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.090s	553.041us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.795m	26.950ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.900s	1.211ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.380s	645.564us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.090s	553.041us	20	20	100.00
		adc_ctrl_csr_aliasing	5.900s	1.211ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.768m	497.242ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.815m	494.652ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.526m	484.752ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.434m	490.636ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.590m	679.807ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.657m	606.348ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	25.264m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.799m	494.059ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.970s	5.329ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.649m	45.822ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.546m	138.253ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	2.201h	3.584s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.820s	493.372us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.880s	527.984us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.370s	491.321us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.370s	491.321us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.200s	974.506us	5	5	100.00
		adc_ctrl_csr_rw	2.090s	553.041us	20	20	100.00
		adc_ctrl_csr_aliasing	5.900s	1.211ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.950s	4.430ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.200s	974.506us	5	5	100.00
		adc_ctrl_csr_rw	2.090s	553.041us	20	20	100.00
		adc_ctrl_csr_aliasing	5.900s	1.211ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.950s	4.430ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	21.550s	8.443ms	5	5	100.00
		adc_ctrl_tl_intg_err	25.480s	9.382ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	25.480s	9.382ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	21.389m	900.260ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.07	96.67	100.00	100.00	98.83	98.33	91.66

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 43.adc_ctrl_filters_both.8459579822867113556001395482373751127508228802593777013296339114463561347452
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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