ADC_CTRL Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.900s	5.927ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.540s	1.304ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.140s	560.650us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	45.380s	53.157ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.490s	1.192ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.470s	624.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.140s	560.650us	20	20	100.00
		adc_ctrl_csr_aliasing	5.490s	1.192ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.690m	492.933ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.168m	490.141ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.591m	498.851ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.021m	497.094ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.019m	591.867ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.155m	618.881ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.331m	544.644ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	20.320m	498.456ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.360s	4.908ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.647m	42.790ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.490m	139.662ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.938m	447.420ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.890s	519.001us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	509.201us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.710s	516.414us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.710s	516.414us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.540s	1.304ms	5	5	100.00
		adc_ctrl_csr_rw	2.140s	560.650us	20	20	100.00
		adc_ctrl_csr_aliasing	5.490s	1.192ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.010s	5.684ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.540s	1.304ms	5	5	100.00
		adc_ctrl_csr_rw	2.140s	560.650us	20	20	100.00
		adc_ctrl_csr_aliasing	5.490s	1.192ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.010s	5.684ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.150s	8.075ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.950s	8.399ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.950s	8.399ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.231m	1.292s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.12

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 1.adc_ctrl_filters_both.72851773143513209450686746915777409814134415482181241904959403737130419918499
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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