ADC_CTRL Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.490s	5.854ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.330s	1.022ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.950s	554.838us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.706m	28.092ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.320s	1.370ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.320s	605.595us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.950s	554.838us	20	20	100.00
		adc_ctrl_csr_aliasing	5.320s	1.370ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.104m	499.447ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.038m	508.694ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.067m	486.812ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.526m	485.321ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.810m	616.173ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.418m	608.085ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.203m	550.780ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	22.101m	528.748ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.850s	4.902ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.773m	41.944ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.837m	126.539ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.941h	3.582s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.930s	528.322us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.020s	518.063us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.750s	590.523us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.750s	590.523us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.330s	1.022ms	5	5	100.00
		adc_ctrl_csr_rw	1.950s	554.838us	20	20	100.00
		adc_ctrl_csr_aliasing	5.320s	1.370ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.490s	4.425ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.330s	1.022ms	5	5	100.00
		adc_ctrl_csr_rw	1.950s	554.838us	20	20	100.00
		adc_ctrl_csr_aliasing	5.320s	1.370ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.490s	4.425ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	19.730s	8.914ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.100s	8.509ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.100s	8.509ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	18.788m	1.066s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			920	920	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.07	96.67	100.00	100.00	98.83	98.33	91.46

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