ADC_CTRL Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.520s	6.095ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.900s	1.294ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.980s	530.601us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.023m	33.227ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.880s	1.280ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.250s	607.368us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.980s	530.601us	20	20	100.00
		adc_ctrl_csr_aliasing	4.880s	1.280ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.857m	500.933ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.808m	494.487ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.497m	487.743ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	17.531m	486.304ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.122m	561.462ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.836m	604.214ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.672m	584.163ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	22.080m	538.706ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.670s	5.507ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.609m	43.076ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.450m	123.220ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.094m	519.707ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.910s	527.701us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	483.685us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.740s	599.284us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.740s	599.284us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.900s	1.294ms	5	5	100.00
		adc_ctrl_csr_rw	1.980s	530.601us	20	20	100.00
		adc_ctrl_csr_aliasing	4.880s	1.280ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.050s	4.738ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.900s	1.294ms	5	5	100.00
		adc_ctrl_csr_rw	1.980s	530.601us	20	20	100.00
		adc_ctrl_csr_aliasing	4.880s	1.280ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.050s	4.738ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	19.220s	8.279ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.190s	8.306ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.190s	8.306ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.328m	780.455ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			916	920	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 19.adc_ctrl_filters_both.81484694642364078802702533780704554046882475987996784480119937668927394492068
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.adc_ctrl_filters_both.1119645727934360802273484063184719018379308602326715589075930005182785922833
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 12.adc_ctrl_stress_all_with_rand_reset.40725717510396084833352802242410510787316178986862483105240742516339876383305
    Line 511, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116033277592 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 56 [0x38]) reg name: adc_ctrl_reg_block.filter_status
  UVM_INFO @ 116033277592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.adc_ctrl_stress_all_with_rand_reset.26335754152322945393347535156220785512956690611841977420579577481255440270149
    Line 504, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 246810887397 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 246810887397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1fbe1ece8d`