ADC_CTRL Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	17.120s	6.086ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.390s	1.131ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.990s	543.763us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.474m	26.019ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.620s	677.269us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.040s	508.057us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.990s	543.763us	20	20	100.00
		adc_ctrl_csr_aliasing	3.620s	677.269us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.883m	488.040ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.498m	487.786ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.655m	499.436ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.651m	492.226ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.189m	631.447ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.819m	595.385ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.391m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.766m	557.975ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.850s	5.333ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.545m	41.405ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.708m	137.718ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.485m	582.278ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.810s	505.414us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	517.982us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.640s	593.935us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.640s	593.935us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.390s	1.131ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	543.763us	20	20	100.00
		adc_ctrl_csr_aliasing	3.620s	677.269us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.840s	4.556ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.390s	1.131ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	543.763us	20	20	100.00
		adc_ctrl_csr_aliasing	3.620s	677.269us	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.840s	4.556ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	11.060s	4.435ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.430s	8.421ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.430s	8.421ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	16.313m	576.467ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 0.adc_ctrl_filters_both.74690651902672378347173803954159119901208935358677782467611515485749938006632
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.adc_ctrl_filters_both.64366743571125354838454073040372826410963811971547869371808028033834326054149
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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