7773b039d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 0 | 50 | 0.00 | ||
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_both | adc_ctrl_filters_both | 0 | 50 | 0.00 | ||
| V2 | clock_gating | adc_ctrl_clock_gating | 0 | 50 | 0.00 | ||
| V2 | poweron_counter | adc_ctrl_poweron_counter | 0 | 50 | 0.00 | ||
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 0 | 50 | 0.00 | ||
| V2 | fsm_reset | adc_ctrl_fsm_reset | 0 | 50 | 0.00 | ||
| V2 | stress_all | adc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | adc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | adc_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 920 failures:
0.adc_ctrl_smoke.58188343246214552423190614105854345819615083192138742914933486813571177199823
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest/run.log
1.adc_ctrl_smoke.53507862830881844788736291772505346827535852480699207072817566943959013011551
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled.23941128780145003201846360137057863526726343230428207360116171052548401743338
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest/run.log
1.adc_ctrl_filters_polled.89404829641397999399237499751117672389014028838288327067019626333011956313761
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled_fixed.6478441991328571349910572282686881272473453265393690924421056568582918688225
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest/run.log
1.adc_ctrl_filters_polled_fixed.1617362256151458517792296322169768986922962996701883011308421338143247790365
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt.113769847363928040594599066894594833914845686197463204682934064269501878195004
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest/run.log
1.adc_ctrl_filters_interrupt.38506872541405195089318158885526835880628690962787336472145989824644811612458
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt_fixed.101806650367069516938774247346223793411283566855276035098311148852692873658513
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest/run.log
1.adc_ctrl_filters_interrupt_fixed.85055625934286728333273834428632595203085121214045008980027515040409288748158
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/cov_report/cov_report.log