1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | adc_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | filters_polled | adc_ctrl_filters_polled | 0 | 50 | 0.00 | ||
| V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt | adc_ctrl_filters_interrupt | 0 | 50 | 0.00 | ||
| V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup | adc_ctrl_filters_wakeup | 0 | 50 | 0.00 | ||
| V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 0 | 50 | 0.00 | ||
| V2 | filters_both | adc_ctrl_filters_both | 0 | 50 | 0.00 | ||
| V2 | clock_gating | adc_ctrl_clock_gating | 0 | 50 | 0.00 | ||
| V2 | poweron_counter | adc_ctrl_poweron_counter | 0 | 50 | 0.00 | ||
| V2 | lowpower_counter | adc_ctrl_lowpower_counter | 0 | 50 | 0.00 | ||
| V2 | fsm_reset | adc_ctrl_fsm_reset | 0 | 50 | 0.00 | ||
| V2 | stress_all | adc_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | adc_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | adc_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| adc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| adc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| adc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 740 | 0.00 | |||
| V2S | tl_intg_err | adc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 920 failures:
0.adc_ctrl_smoke.1553459895494694591786540645376254247690635622560366026043111058067744638138
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest/run.log
1.adc_ctrl_smoke.54968643538620257064269312476944551009850668739238574994223135350814948463916
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled.61926345428583314488480132376152827749541745144278928075206619787404228047333
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest/run.log
1.adc_ctrl_filters_polled.71704102141968149311249338833560266630494000427963899140999323122181919922615
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_polled_fixed.73174081133497974800555258158514837087915598865363104549210589810445953669326
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest/run.log
1.adc_ctrl_filters_polled_fixed.101457232150336894770551304560701366605886285482209435822855780784311275249922
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt.87232845003199709736625157371719208852034115823385932045981122651525456472944
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest/run.log
1.adc_ctrl_filters_interrupt.53369406459883479591273720846878670465475175552290038940791127381173233030120
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest/run.log
... and 48 more failures.
0.adc_ctrl_filters_interrupt_fixed.91120629653218653956419988220523057544137144613854426901598248792706390687229
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest/run.log
1.adc_ctrl_filters_interrupt_fixed.24993258279619960443677935851639375066832369217786153909153658926295596434006
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/cov_report/cov_report.log