ADC_CTRL Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.990s 6.202ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 4.130s 1.333ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.110s 529.392us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.326m 53.071ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 3.550s 1.170ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.590s 606.221us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.110s 529.392us 20 20 100.00
adc_ctrl_csr_aliasing 3.550s 1.170ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.988m 490.427ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.272m 499.491ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.211m 488.426ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.348m 489.301ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 21.887m 528.774ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.740m 607.499ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 22.639m 600.000ms 47 50 94.00
V2 clock_gating adc_ctrl_clock_gating 21.146m 592.619ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 14.200s 5.326ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.838m 45.699ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.460m 143.103ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 1.187h 1.759s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.880s 528.016us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 2.080s 528.729us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 4.120s 655.184us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 4.120s 655.184us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 4.130s 1.333ms 5 5 100.00
adc_ctrl_csr_rw 2.110s 529.392us 20 20 100.00
adc_ctrl_csr_aliasing 3.550s 1.170ms 5 5 100.00
adc_ctrl_same_csr_outstanding 12.690s 5.353ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 4.130s 1.333ms 5 5 100.00
adc_ctrl_csr_rw 2.110s 529.392us 20 20 100.00
adc_ctrl_csr_aliasing 3.550s 1.170ms 5 5 100.00
adc_ctrl_same_csr_outstanding 12.690s 5.353ms 20 20 100.00
V2 TOTAL 737 740 99.59
V2S tl_intg_err adc_ctrl_sec_cm 20.370s 8.180ms 5 5 100.00
adc_ctrl_tl_intg_err 25.300s 8.977ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 25.300s 8.977ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 10.847m 349.957ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 917 920 99.67

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 15 93.75
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.51

Failure Buckets

Past Results