ADC_CTRL Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.890s	5.957ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.800s	1.199ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.040s	527.203us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.211m	17.121ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.020s	1.167ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.270s	606.282us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.040s	527.203us	20	20	100.00
		adc_ctrl_csr_aliasing	5.020s	1.167ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.180m	497.596ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.954m	502.367ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.354m	484.182ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.891m	492.178ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.558m	579.813ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.738m	595.234ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.171m	515.736ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	24.335m	592.426ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.800s	4.828ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.629m	41.633ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.701m	142.673ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	42.997m	533.666ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.870s	524.996us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	531.837us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.320s	480.280us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.320s	480.280us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.800s	1.199ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	527.203us	20	20	100.00
		adc_ctrl_csr_aliasing	5.020s	1.167ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.570s	4.336ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.800s	1.199ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	527.203us	20	20	100.00
		adc_ctrl_csr_aliasing	5.020s	1.167ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.570s	4.336ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	16.550s	7.385ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.590s	8.233ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.590s	8.233ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	23.786m	747.832ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	99.07	96.67	100.00	100.00	98.83	98.33	90.37

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 18.adc_ctrl_filters_both.43107010202442115437027567260395448459625697286128960674482128110023083163500
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 49.adc_ctrl_stress_all_with_rand_reset.54755240886748000564247112410853860172407755928470066260347467504633887181541
    Line 388, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26415713869 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 26415713869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `00fe426038`