ADC_CTRL Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.820s	5.915ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.250s	1.104ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.940s	411.520us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.960m	27.398ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.650s	1.055ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.350s	600.792us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.940s	411.520us	20	20	100.00
		adc_ctrl_csr_aliasing	5.650s	1.055ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.076m	491.602ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	13.082m	323.005ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.752m	496.124ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.324m	492.527ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.320m	596.781ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.880m	595.200ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.621m	552.871ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.764m	502.151ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.470s	5.609ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.820m	46.894ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.226m	130.043ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.021m	552.560ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.940s	531.684us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.890s	496.619us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.690s	764.823us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.690s	764.823us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.250s	1.104ms	5	5	100.00
		adc_ctrl_csr_rw	1.940s	411.520us	20	20	100.00
		adc_ctrl_csr_aliasing	5.650s	1.055ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.430s	4.313ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.250s	1.104ms	5	5	100.00
		adc_ctrl_csr_rw	1.940s	411.520us	20	20	100.00
		adc_ctrl_csr_aliasing	5.650s	1.055ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.430s	4.313ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	19.060s	8.714ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.360s	8.506ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.360s	8.506ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.029m	4.309s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.07	96.67	100.00	100.00	98.83	98.33	90.99

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 36.adc_ctrl_stress_all_with_rand_reset.11751030626977433502153993736104083513493310831268469651067414799070185261432
      Line 355, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64848445841 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 64848445841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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