ADC_CTRL Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.300s	6.028ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.200s	1.096ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	513.585us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.624m	49.487ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.010s	1.325ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.400s	670.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	513.585us	20	20	100.00
		adc_ctrl_csr_aliasing	4.010s	1.325ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.711m	486.553ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.275m	490.258ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.505m	492.278ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.430m	495.167ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.237m	574.571ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.221m	606.212ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.077m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.852m	529.711ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.670s	5.357ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.850m	47.067ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.940m	138.378ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	22.639m	706.394ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.890s	517.989us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	474.207us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.130s	613.188us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.130s	613.188us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.200s	1.096ms	5	5	100.00
		adc_ctrl_csr_rw	1.920s	513.585us	20	20	100.00
		adc_ctrl_csr_aliasing	4.010s	1.325ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.520s	4.984ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.200s	1.096ms	5	5	100.00
		adc_ctrl_csr_rw	1.920s	513.585us	20	20	100.00
		adc_ctrl_csr_aliasing	4.010s	1.325ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.520s	4.984ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	18.970s	8.216ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.800s	7.740ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.800s	7.740ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.750m	705.905ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.07	96.67	100.00	100.00	98.83	98.33	91.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 9.adc_ctrl_filters_both.89447595481917472499977451548616310971877951312780591991036678569401324545283
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.adc_ctrl_filters_both.2489946172686068914124765287340245754142317542115464777181593550898340194663
      Line 363, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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