ADC_CTRL Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.750s	6.067ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.720s	886.452us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	496.069us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	46.710s	26.981ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.160s	1.111ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.490s	597.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	496.069us	20	20	100.00
		adc_ctrl_csr_aliasing	3.160s	1.111ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.138m	483.894ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.012m	496.213ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.886m	491.034ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.215m	497.674ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.519m	562.602ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.763m	591.721ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.639m	561.854ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.348m	545.109ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.440s	5.130ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.711m	44.215ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.640m	143.326ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	21.089m	429.213ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	515.660us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	512.826us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.760s	477.691us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.760s	477.691us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.720s	886.452us	5	5	100.00
		adc_ctrl_csr_rw	1.920s	496.069us	20	20	100.00
		adc_ctrl_csr_aliasing	3.160s	1.111ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.670s	4.265ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.720s	886.452us	5	5	100.00
		adc_ctrl_csr_rw	1.920s	496.069us	20	20	100.00
		adc_ctrl_csr_aliasing	3.160s	1.111ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.670s	4.265ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	9.400s	4.005ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.670s	8.837ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.670s	8.837ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.286m	456.295ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.07	96.67	100.00	100.00	98.83	98.33	91.56

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 12.adc_ctrl_filters_both.19305997589807643769942209754002147445427441421854041228756648183096551370708
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.adc_ctrl_filters_both.22748625724262710955211827197740283007745285775345479754463403350783478737691
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.05.20_03.46.07
• 2024.05.17_06.14.23
• 2024.05.15_02.42.51
• 2024.05.13_03.31.19
• 2024.05.10_04.15.43
• 2024.05.08_03.25.07