ADC_CTRL Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.010s	5.976ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.170s	1.145ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.220s	554.714us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	23.630s	22.897ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.850s	1.319ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.530s	665.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.220s	554.714us	20	20	100.00
		adc_ctrl_csr_aliasing	5.850s	1.319ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.761m	499.151ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.511m	488.528ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.417m	493.179ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.671m	499.719ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.421m	565.569ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.959m	607.792ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.994m	569.117ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.787m	547.081ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.720s	5.692ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.765m	45.705ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.649m	132.333ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.086h	3.904s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	532.222us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.010s	516.931us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.710s	574.171us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.710s	574.171us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.170s	1.145ms	5	5	100.00
		adc_ctrl_csr_rw	2.220s	554.714us	20	20	100.00
		adc_ctrl_csr_aliasing	5.850s	1.319ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.420s	5.313ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.170s	1.145ms	5	5	100.00
		adc_ctrl_csr_rw	2.220s	554.714us	20	20	100.00
		adc_ctrl_csr_aliasing	5.850s	1.319ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.420s	5.313ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.250s	4.482ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.450s	8.606ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.450s	8.606ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	14.387m	551.738ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			920	920	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.14

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