ADC_CTRL Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.870s	5.962ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.450s	1.113ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.300s	576.191us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.716m	46.536ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.970s	824.694us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.410s	582.765us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.300s	576.191us	20	20	100.00
		adc_ctrl_csr_aliasing	3.970s	824.694us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.395m	486.133ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.665m	488.407ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.863m	492.019ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.949m	498.311ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.889m	546.151ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.011m	616.240ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.425m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	15.833m	540.963ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.750s	5.548ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.661m	44.221ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.732m	128.131ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.151h	4.086s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.830s	507.944us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.960s	488.571us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.220s	675.175us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.220s	675.175us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.450s	1.113ms	5	5	100.00
		adc_ctrl_csr_rw	2.300s	576.191us	20	20	100.00
		adc_ctrl_csr_aliasing	3.970s	824.694us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.030s	5.031ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.450s	1.113ms	5	5	100.00
		adc_ctrl_csr_rw	2.300s	576.191us	20	20	100.00
		adc_ctrl_csr_aliasing	3.970s	824.694us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.030s	5.031ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	9.780s	7.864ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.710s	8.603ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.710s	8.603ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.342m	516.175ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.32

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 11.adc_ctrl_filters_both.86971653256608420196248212549314930254404918413533631195566872926196927230943
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.adc_ctrl_filters_both.60856674536105568782100513717814965519627615739854810122501913455174992570121
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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