ADC_CTRL Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.770s	5.772ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.600s	1.253ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.040s	527.584us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.849m	52.474ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.390s	1.090ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.280s	512.665us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.040s	527.584us	20	20	100.00
		adc_ctrl_csr_aliasing	4.390s	1.090ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.753m	493.921ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.979m	495.396ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.984m	502.478ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.526m	491.906ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.664m	582.863ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.234m	598.718ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	24.338m	581.572ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	16.988m	522.379ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.020s	5.432ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.838m	45.499ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.476m	124.872ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	58.211m	1.440s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.960s	533.066us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.900s	508.163us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.710s	605.135us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.710s	605.135us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.600s	1.253ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	527.584us	20	20	100.00
		adc_ctrl_csr_aliasing	4.390s	1.090ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.220s	5.303ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.600s	1.253ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	527.584us	20	20	100.00
		adc_ctrl_csr_aliasing	4.390s	1.090ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.220s	5.303ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	19.730s	7.932ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.510s	8.377ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.510s	8.377ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.366m	278.538ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.07	96.67	100.00	100.00	98.83	98.33	91.59

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 0.adc_ctrl_filters_both.99574179438072039989085518898920360174847610346077540563538377801853427514190
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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