ADC_CTRL Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.740s 5.591ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.670s 860.163us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.070s 517.174us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 2.154m 52.420ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 5.350s 1.292ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.240s 529.526us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.070s 517.174us 20 20 100.00
adc_ctrl_csr_aliasing 5.350s 1.292ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.371m 491.736ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.791m 493.251ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.299m 493.996ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.227m 493.752ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 25.191m 618.171ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.274m 602.958ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 21.491m 526.802ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 23.869m 696.322ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.470s 5.307ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.898m 47.075ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 12.962m 138.865ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 41.269m 772.993ms 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.880s 521.707us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 2.020s 481.500us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.600s 605.830us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.600s 605.830us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.670s 860.163us 5 5 100.00
adc_ctrl_csr_rw 2.070s 517.174us 20 20 100.00
adc_ctrl_csr_aliasing 5.350s 1.292ms 5 5 100.00
adc_ctrl_same_csr_outstanding 22.860s 5.629ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.670s 860.163us 5 5 100.00
adc_ctrl_csr_rw 2.070s 517.174us 20 20 100.00
adc_ctrl_csr_aliasing 5.350s 1.292ms 5 5 100.00
adc_ctrl_same_csr_outstanding 22.860s 5.629ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 20.300s 7.965ms 5 5 100.00
adc_ctrl_tl_intg_err 22.730s 8.149ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.730s 8.149ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 14.706m 810.422ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92

Past Results