ADC_CTRL Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.980s	5.723ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.690s	1.248ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.970s	465.370us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.994m	52.566ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.930s	1.238ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.290s	604.587us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.970s	465.370us	20	20	100.00
		adc_ctrl_csr_aliasing	5.930s	1.238ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.173m	489.329ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.707m	485.059ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.209m	490.094ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.312m	501.529ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.835m	613.540ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.316m	598.438ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.195m	593.618ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	21.383m	624.700ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.180s	5.362ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.907m	45.130ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.731m	136.382ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	22.921m	455.427ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.660s	437.898us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	518.610us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.010s	510.513us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.010s	510.513us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.690s	1.248ms	5	5	100.00
		adc_ctrl_csr_rw	1.970s	465.370us	20	20	100.00
		adc_ctrl_csr_aliasing	5.930s	1.238ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.670s	4.340ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.690s	1.248ms	5	5	100.00
		adc_ctrl_csr_rw	1.970s	465.370us	20	20	100.00
		adc_ctrl_csr_aliasing	5.930s	1.238ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	21.670s	4.340ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	11.200s	8.394ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.410s	7.763ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.410s	7.763ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.989m	383.442ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			920	920	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.07	96.67	100.00	100.00	98.83	98.33	90.92

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