ADC_CTRL Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.030s	6.133ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.200s	1.401ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	499.954us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.979m	22.312ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.220s	1.233ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.060s	474.571us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	499.954us	20	20	100.00
		adc_ctrl_csr_aliasing	5.220s	1.233ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.686m	491.917ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.511m	499.912ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.515m	497.346ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.081m	492.780ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.205m	527.346ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.284m	592.238ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	25.044m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	15.542m	592.384ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.070s	5.512ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.781m	44.059ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	13.153m	154.049ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.171h	1.649s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.840s	507.070us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.880s	456.051us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.710s	516.057us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.710s	516.057us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.200s	1.401ms	5	5	100.00
		adc_ctrl_csr_rw	1.920s	499.954us	20	20	100.00
		adc_ctrl_csr_aliasing	5.220s	1.233ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.090s	5.411ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.200s	1.401ms	5	5	100.00
		adc_ctrl_csr_rw	1.920s	499.954us	20	20	100.00
		adc_ctrl_csr_aliasing	5.220s	1.233ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.090s	5.411ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	10.680s	8.116ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.910s	8.658ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.910s	8.658ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.084m	222.938ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.17

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 4.adc_ctrl_filters_both.53794534989557129338282496331819876230458971726064971491922380508730985770523
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.adc_ctrl_filters_both.15535416720566235238221937148438922179205934326889830061437965537180918482291
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.06.03_06.41.55
• 2024.05.31_04.33.32
• 2024.05.29_02.59.40
• 2024.05.27_04.10.21
• 2024.05.24_04.15.46
• 2024.05.22_04.13.31