ADC_CTRL Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.140s	6.070ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.530s	918.749us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.980s	524.391us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.068m	23.860ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.820s	1.090ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.460s	613.118us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.980s	524.391us	20	20	100.00
		adc_ctrl_csr_aliasing	4.820s	1.090ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.582m	492.937ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.120m	504.313ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.268m	489.937ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.466m	488.474ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.893m	581.528ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.399m	599.172ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.263m	524.279ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.149m	530.651ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.580s	5.079ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.798m	45.417ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.747m	131.230ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	30.458m	322.811ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.890s	529.777us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.980s	525.463us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.190s	622.655us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.190s	622.655us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.530s	918.749us	5	5	100.00
		adc_ctrl_csr_rw	1.980s	524.391us	20	20	100.00
		adc_ctrl_csr_aliasing	4.820s	1.090ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.010s	4.508ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.530s	918.749us	5	5	100.00
		adc_ctrl_csr_rw	1.980s	524.391us	20	20	100.00
		adc_ctrl_csr_aliasing	4.820s	1.090ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.010s	4.508ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	19.560s	8.087ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.320s	8.182ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.320s	8.182ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.108m	429.337ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.07	96.67	100.00	100.00	98.83	98.33	91.27

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_filters_both has 2 failures.

    • 15.adc_ctrl_filters_both.74901027851981681502582359715966935832290792520950625688319450205230461608321
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.adc_ctrl_filters_both.95925387593198458081070970901580800715074402521633454800774321947182083729656
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.06.05_03.36.24
• 2024.06.03_06.41.55
• 2024.05.31_04.33.32
• 2024.05.29_02.59.40
• 2024.05.27_04.10.21
• 2024.05.24_04.15.46