ADC_CTRL Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.550s	5.906ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.360s	752.367us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.050s	556.318us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	4.290m	52.496ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.590s	1.147ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.260s	597.815us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.050s	556.318us	20	20	100.00
		adc_ctrl_csr_aliasing	3.590s	1.147ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.582m	496.595ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.860m	488.828ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.350m	489.039ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.493m	491.414ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.041m	559.785ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.165m	600.087ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.723m	535.789ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.126m	593.197ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.020s	5.531ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.778m	45.315ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.102m	145.329ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.332m	416.181ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.810s	500.473us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.960s	508.265us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.700s	544.099us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.700s	544.099us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.360s	752.367us	5	5	100.00
		adc_ctrl_csr_rw	2.050s	556.318us	20	20	100.00
		adc_ctrl_csr_aliasing	3.590s	1.147ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	9.170s	1.983ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.360s	752.367us	5	5	100.00
		adc_ctrl_csr_rw	2.050s	556.318us	20	20	100.00
		adc_ctrl_csr_aliasing	3.590s	1.147ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	9.170s	1.983ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	19.840s	8.455ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.320s	7.930ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.320s	7.930ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.001m	386.341ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.81	99.07	96.67	100.00	100.00	98.83	98.33	91.76

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.adc_ctrl_stress_all_with_rand_reset.98988794982845974915786935649699314691260969058285374537711894064620604544118
      Line 496, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 109021174931 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 96 [0x60]) reg name: adc_ctrl_reg_block.filter_status
        UVM_INFO @ 109021174931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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