ADC_CTRL Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.240s	5.745ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.000s	957.935us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.030s	451.737us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.981m	42.110ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.140s	1.240ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.290s	613.214us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.030s	451.737us	20	20	100.00
		adc_ctrl_csr_aliasing	6.140s	1.240ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.432m	500.554ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.270m	497.867ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.256m	481.815ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.168m	487.605ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.065m	560.422ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	26.092m	630.994ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.223m	529.814ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.451m	525.580ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.280s	5.358ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.801m	43.091ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.110m	134.724ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	54.578m	1.145s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.850s	527.507us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.800s	474.867us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.230s	793.788us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.230s	793.788us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.000s	957.935us	5	5	100.00
		adc_ctrl_csr_rw	2.030s	451.737us	20	20	100.00
		adc_ctrl_csr_aliasing	6.140s	1.240ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.500s	5.227ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.000s	957.935us	5	5	100.00
		adc_ctrl_csr_rw	2.030s	451.737us	20	20	100.00
		adc_ctrl_csr_aliasing	6.140s	1.240ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.500s	5.227ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	18.240s	7.447ms	5	5	100.00
		adc_ctrl_tl_intg_err	13.090s	8.478ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	13.090s	8.478ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.234m	397.074ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.07	96.67	100.00	100.00	98.83	98.33	91.04

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 47.adc_ctrl_stress_all_with_rand_reset.27513222978313124570621417381835894969542590449287614198980662463729600300328
      Line 372, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 49737244115 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: adc_ctrl_reg_block.filter_status
        UVM_INFO @ 49737244115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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