ADC_CTRL Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.990s	6.013ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.580s	1.187ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.130s	524.098us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.467m	45.695ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.420s	906.247us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.540s	657.784us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.130s	524.098us	20	20	100.00
		adc_ctrl_csr_aliasing	3.420s	906.247us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.065m	490.557ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.221m	501.097ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.809m	502.035ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.375m	496.769ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.855m	703.340ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.278m	611.322ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	25.826m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.755m	501.116ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.760s	4.967ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.890m	45.757ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.911m	130.825ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.846m	491.828ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	489.421us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	483.672us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.260s	497.340us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.260s	497.340us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.580s	1.187ms	5	5	100.00
		adc_ctrl_csr_rw	2.130s	524.098us	20	20	100.00
		adc_ctrl_csr_aliasing	3.420s	906.247us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.280s	4.414ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.580s	1.187ms	5	5	100.00
		adc_ctrl_csr_rw	2.130s	524.098us	20	20	100.00
		adc_ctrl_csr_aliasing	3.420s	906.247us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.280s	4.414ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	20.530s	8.024ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.590s	8.299ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.590s	8.299ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.245m	692.494ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 3.adc_ctrl_filters_both.106661046825335271361963113608964927104712397894649579638936187826816069172056
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.adc_ctrl_stress_all_with_rand_reset.18106522612476111863418563748749560481966168306110591421247143502500796363338
    Line 401, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16127855984 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 16127855984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f92a5ee77b`