ADC_CTRL Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.690s	5.842ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.410s	1.198ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.010s	513.088us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.821m	52.534ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.990s	1.276ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.190s	524.346us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.010s	513.088us	20	20	100.00
		adc_ctrl_csr_aliasing	4.990s	1.276ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.170m	500.771ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.331m	492.826ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.347m	492.189ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.088m	495.018ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.464m	652.156ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	25.178m	622.022ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.899m	543.306ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	22.672m	537.242ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.600s	5.324ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.976m	47.449ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.252m	141.941ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.932m	662.274ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.760s	464.507us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	506.860us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.940s	627.741us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.940s	627.741us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.410s	1.198ms	5	5	100.00
		adc_ctrl_csr_rw	2.010s	513.088us	20	20	100.00
		adc_ctrl_csr_aliasing	4.990s	1.276ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.730s	4.689ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.410s	1.198ms	5	5	100.00
		adc_ctrl_csr_rw	2.010s	513.088us	20	20	100.00
		adc_ctrl_csr_aliasing	4.990s	1.276ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.730s	4.689ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.980s	4.207ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.840s	8.568ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.840s	8.568ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	27.180m	1.313s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 17.adc_ctrl_stress_all_with_rand_reset.92323387985258707814492675545057697763391246530842937183824615687556912058332
      Line 392, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17893352337 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 6 [0x6]) reg name: adc_ctrl_reg_block.filter_status
        UVM_INFO @ 17893352337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.06.10_06.24.51
• 2024.06.08_12.53.01
• 2024.06.07_04.35.57
• 2024.06.06_10.46.50
• 2024.06.05_03.36.24
• 2024.06.03_06.41.55