ADC_CTRL Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	17.240s	5.822ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.150s	1.420ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.000s	533.264us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.762m	53.194ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.990s	1.306ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.440s	619.488us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.000s	533.264us	20	20	100.00
		adc_ctrl_csr_aliasing	2.990s	1.306ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.655m	506.387ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	21.245m	486.002ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.085m	493.792ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	21.467m	489.199ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	27.703m	689.742ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	26.968m	600.632ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	25.090m	553.013ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	22.665m	528.445ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.090s	5.422ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.743m	45.729ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	13.268m	140.524ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	32.200m	1.262s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.890s	513.978us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.820s	482.627us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.400s	1.220ms	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.400s	1.220ms	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.150s	1.420ms	5	5	100.00
		adc_ctrl_csr_rw	2.000s	533.264us	20	20	100.00
		adc_ctrl_csr_aliasing	2.990s	1.306ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.020s	4.131ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.150s	1.420ms	5	5	100.00
		adc_ctrl_csr_rw	2.000s	533.264us	20	20	100.00
		adc_ctrl_csr_aliasing	2.990s	1.306ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.020s	4.131ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	11.620s	7.550ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.740s	8.587ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.740s	8.587ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	18.185m	923.682ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.07	96.67	100.00	100.00	98.83	98.33	91.39

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 4.adc_ctrl_filters_both.95462552146896043174330036951337931093030014035445254050409867618266379290049
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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