ADC_CTRL Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.090s	5.903ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.890s	1.039ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.920s	535.348us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.097m	39.638ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.290s	1.191ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.190s	582.427us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.920s	535.348us	20	20	100.00
		adc_ctrl_csr_aliasing	5.290s	1.191ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.715m	503.263ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.805m	504.778ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.492m	490.331ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.929m	488.724ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.188m	643.284ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.351m	594.628ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.842m	589.541ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	19.602m	533.162ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.920s	5.326ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.845m	46.377ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.512m	130.842ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	45.901m	1.057s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.760s	513.969us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	521.055us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.650s	408.116us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.650s	408.116us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.890s	1.039ms	5	5	100.00
		adc_ctrl_csr_rw	1.920s	535.348us	20	20	100.00
		adc_ctrl_csr_aliasing	5.290s	1.191ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.780s	5.173ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.890s	1.039ms	5	5	100.00
		adc_ctrl_csr_rw	1.920s	535.348us	20	20	100.00
		adc_ctrl_csr_aliasing	5.290s	1.191ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.780s	5.173ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	19.710s	8.175ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.610s	8.215ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.610s	8.215ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.464m	506.940ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.07	96.67	100.00	100.00	98.83	98.33	91.39

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 26.adc_ctrl_filters_both.84129183830928606285150604359125591562380089249149244518322249388812765422804
    Line 363, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.adc_ctrl_filters_both.8012001160905390630486255102082804703639178091956301996934722638824500168119
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 20.adc_ctrl_stress_all_with_rand_reset.112724093699836563338140936936709503094624695231819598383414708657248831127852
    Line 421, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 15032772469 ps: (adc_ctrl_fsm.sv:384) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 15032772469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `548a3880d8`