ADC_CTRL Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: de38ce313c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.330s	5.960ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.840s	1.032ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.990s	514.261us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.003m	23.325ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.680s	1.238ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.120s	573.068us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.990s	514.261us	20	20	100.00
		adc_ctrl_csr_aliasing	5.680s	1.238ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.125m	490.814ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.650m	496.887ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.259m	493.165ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.501m	496.118ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.277m	645.969ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.677m	614.714ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.854m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	20.412m	523.439ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.110s	5.498ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.651m	43.312ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.818m	146.596ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	30.089m	544.114ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.820s	505.673us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	509.548us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.230s	412.728us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.230s	412.728us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.840s	1.032ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	514.261us	20	20	100.00
		adc_ctrl_csr_aliasing	5.680s	1.238ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.690s	5.161ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.840s	1.032ms	5	5	100.00
		adc_ctrl_csr_rw	1.990s	514.261us	20	20	100.00
		adc_ctrl_csr_aliasing	5.680s	1.238ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.690s	5.161ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	19.640s	7.980ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.140s	8.504ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.140s	8.504ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.658m	394.903ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.07	96.67	100.00	100.00	98.83	98.33	90.79

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test adc_ctrl_filters_both has 2 failures.

    • 8.adc_ctrl_filters_both.106310304169460273301366779110582779746453593943640624796341986037034029144897
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.adc_ctrl_filters_both.69219020371703884018360410362059768348413149576982362597377347656207197317955
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.filter_status has 1 failures:

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 16.adc_ctrl_stress_all_with_rand_reset.24676632612294730787829775497160041205237850197698134298858886385772372803621
      Line 387, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 116848597786 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: adc_ctrl_reg_block.filter_status
        UVM_INFO @ 116848597786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.06.14_06.59.53
• 2024.06.12_04.36.18
• 2024.06.11_11.40.42
• 2024.06.10_06.24.51
• 2024.06.08_12.53.01
• 2024.06.07_04.35.57