ADC_CTRL Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.300s	5.948ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.440s	796.895us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.180s	569.288us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.236m	23.568ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.650s	1.035ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	497.701us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.180s	569.288us	20	20	100.00
		adc_ctrl_csr_aliasing	4.650s	1.035ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.012m	488.513ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.964m	498.044ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.553m	492.822ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.496m	489.991ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	21.491m	530.949ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.449m	619.833ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.311m	560.806ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	17.940m	607.908ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	11.980s	4.792ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.673m	42.164ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.738m	133.375ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	55.569m	1.330s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.780s	485.962us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.750s	513.442us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.230s	714.140us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.230s	714.140us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.440s	796.895us	5	5	100.00
		adc_ctrl_csr_rw	2.180s	569.288us	20	20	100.00
		adc_ctrl_csr_aliasing	4.650s	1.035ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.730s	4.370ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.440s	796.895us	5	5	100.00
		adc_ctrl_csr_rw	2.180s	569.288us	20	20	100.00
		adc_ctrl_csr_aliasing	4.650s	1.035ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.730s	4.370ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	9.500s	3.976ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.570s	8.461ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.570s	8.461ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.878m	395.919ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.07	96.67	100.00	100.00	98.83	98.33	91.39

Failure Buckets

UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.adc_ctrl_stress_all_with_rand_reset.86089567683850978985815596021702511375593182096533510979590671827879039059834
    Line 421, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1185626094573 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1185626094573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 45.adc_ctrl_filters_both.80859309860058160113920232601845110438988742449571868529231058842001575114485
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8fdb25c8d9`