ADC_CTRL Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.290s	5.901ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.320s	1.347ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.050s	521.553us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.994m	38.694ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.530s	1.228ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.430s	644.516us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.050s	521.553us	20	20	100.00
		adc_ctrl_csr_aliasing	3.530s	1.228ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.790m	500.429ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.521m	492.588ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.370m	493.767ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.933m	498.230ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.779m	588.611ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.685m	585.066ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.022m	491.588ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.512m	620.270ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.570s	5.201ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.584m	44.954ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.629m	138.832ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	33.004m	838.615ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.900s	533.454us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.840s	535.743us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.670s	1.117ms	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.670s	1.117ms	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.320s	1.347ms	5	5	100.00
		adc_ctrl_csr_rw	2.050s	521.553us	20	20	100.00
		adc_ctrl_csr_aliasing	3.530s	1.228ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.050s	5.612ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.320s	1.347ms	5	5	100.00
		adc_ctrl_csr_rw	2.050s	521.553us	20	20	100.00
		adc_ctrl_csr_aliasing	3.530s	1.228ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.050s	5.612ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	10.330s	4.096ms	5	5	100.00
		adc_ctrl_tl_intg_err	20.520s	8.144ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20.520s	8.144ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	15.505m	1.185s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.07	96.67	100.00	100.00	98.83	98.33	91.59

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 39.adc_ctrl_filters_both.1671756851464842141812461487204238792851753535921744442317250494135674321676
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.adc_ctrl_filters_both.105976339070664588484774470472623974427115118412153317462218784815337442393277
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25e609d6bb`