ADC_CTRL Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	14.740s	6.022ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.420s	1.127ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.160s	552.832us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	51.670s	20.162ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.710s	1.112ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.390s	643.806us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.160s	552.832us	20	20	100.00
		adc_ctrl_csr_aliasing	4.710s	1.112ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.738m	494.226ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.154m	509.609ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	18.916m	484.620ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.825m	491.298ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.002m	651.256ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.771m	587.961ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.467m	532.343ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.096m	505.835ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.000s	5.418ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.641m	46.651ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.822m	131.535ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	2.320h	3.767s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.740s	469.870us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.790s	493.891us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.740s	470.966us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.740s	470.966us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.420s	1.127ms	5	5	100.00
		adc_ctrl_csr_rw	2.160s	552.832us	20	20	100.00
		adc_ctrl_csr_aliasing	4.710s	1.112ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.620s	5.355ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.420s	1.127ms	5	5	100.00
		adc_ctrl_csr_rw	2.160s	552.832us	20	20	100.00
		adc_ctrl_csr_aliasing	4.710s	1.112ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.620s	5.355ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.080s	4.202ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.690s	9.127ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.690s	9.127ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.579m	293.260ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			920	920	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.67	100.00	100.00	98.83	98.33	91.34

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