ADC_CTRL Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.360s	6.132ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.380s	1.251ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.040s	508.009us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.672m	25.323ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.880s	1.163ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.360s	659.049us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.040s	508.009us	20	20	100.00
		adc_ctrl_csr_aliasing	5.880s	1.163ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.162m	487.751ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.754m	492.066ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.016m	498.416ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.868m	494.713ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.906m	603.543ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.736m	612.141ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.115m	571.806ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.238m	508.762ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	15.180s	5.243ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.759m	46.571ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.236m	139.507ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.077m	718.469ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.780s	519.914us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.740s	476.047us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.710s	459.591us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.710s	459.591us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.380s	1.251ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	508.009us	20	20	100.00
		adc_ctrl_csr_aliasing	5.880s	1.163ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.160s	5.390ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.380s	1.251ms	5	5	100.00
		adc_ctrl_csr_rw	2.040s	508.009us	20	20	100.00
		adc_ctrl_csr_aliasing	5.880s	1.163ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.160s	5.390ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	19.440s	7.648ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.090s	8.533ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.090s	8.533ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.769m	492.709ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			920	920	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.07	96.62	100.00	100.00	98.83	98.33	91.42

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