ADC_CTRL Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.690s	6.135ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.800s	963.410us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.000s	564.602us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.529m	35.467ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.030s	1.115ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.190s	492.456us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.000s	564.602us	20	20	100.00
		adc_ctrl_csr_aliasing	5.030s	1.115ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.393m	490.794ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.538m	489.983ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.414m	490.179ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.872m	490.416ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.207m	665.140ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	22.873m	596.770ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.309m	510.840ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.102m	589.405ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.980s	5.674ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.844m	46.963ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.689m	132.914ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	27.126m	1.983s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.740s	475.109us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	529.364us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.360s	715.564us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.360s	715.564us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.800s	963.410us	5	5	100.00
		adc_ctrl_csr_rw	2.000s	564.602us	20	20	100.00
		adc_ctrl_csr_aliasing	5.030s	1.115ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.080s	4.909ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.800s	963.410us	5	5	100.00
		adc_ctrl_csr_rw	2.000s	564.602us	20	20	100.00
		adc_ctrl_csr_aliasing	5.030s	1.115ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	16.080s	4.909ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	21.120s	8.322ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.050s	8.242ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.050s	8.242ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.732m	872.566ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.07	96.67	100.00	100.00	98.83	98.33	91.51

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 11.adc_ctrl_filters_both.53241072836388184755947196786837896178401030639264974033167285715540920120415
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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