ADC_CTRL Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 16.470s 6.153ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.040s 775.742us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.810s 388.881us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 35.000s 25.956ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.510s 965.307us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.330s 562.044us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.810s 388.881us 20 20 100.00
adc_ctrl_csr_aliasing 4.510s 965.307us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.438m 492.277ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.185m 495.893ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.861m 497.178ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.679m 486.402ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 22.630m 563.181ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 24.034m 613.422ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.389m 563.822ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 19.453m 524.045ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.120s 5.334ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.815m 45.285ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.409m 141.910ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 35.263m 3.948s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.880s 526.229us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.870s 502.529us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.660s 574.358us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.660s 574.358us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.040s 775.742us 5 5 100.00
adc_ctrl_csr_rw 1.810s 388.881us 20 20 100.00
adc_ctrl_csr_aliasing 4.510s 965.307us 5 5 100.00
adc_ctrl_same_csr_outstanding 18.730s 4.726ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.040s 775.742us 5 5 100.00
adc_ctrl_csr_rw 1.810s 388.881us 20 20 100.00
adc_ctrl_csr_aliasing 4.510s 965.307us 5 5 100.00
adc_ctrl_same_csr_outstanding 18.730s 4.726ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 19.860s 8.532ms 5 5 100.00
adc_ctrl_tl_intg_err 21.700s 8.485ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 21.700s 8.485ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 18.396m 929.144ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 920 920 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.17

Past Results