ADC_CTRL Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.490s	6.090ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.250s	678.724us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.090s	527.106us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.445m	48.325ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.170s	1.439ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.180s	586.875us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.090s	527.106us	20	20	100.00
		adc_ctrl_csr_aliasing	3.170s	1.439ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.680m	492.128ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.780m	494.182ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.055m	497.304ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.516m	502.052ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.629m	606.221ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	24.324m	614.711ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.299m	542.894ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.384m	528.952ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.220s	4.922ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.671m	47.222ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.798m	143.607ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	38.877m	1.046s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.800s	496.123us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.800s	514.944us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.520s	427.466us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.520s	427.466us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.250s	678.724us	5	5	100.00
		adc_ctrl_csr_rw	2.090s	527.106us	20	20	100.00
		adc_ctrl_csr_aliasing	3.170s	1.439ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.620s	4.472ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.250s	678.724us	5	5	100.00
		adc_ctrl_csr_rw	2.090s	527.106us	20	20	100.00
		adc_ctrl_csr_aliasing	3.170s	1.439ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	17.620s	4.472ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.840s	7.941ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.770s	8.458ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.770s	8.458ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.091m	420.709ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.22

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.adc_ctrl_stress_all_with_rand_reset.36991452055632602747314758166013290421534694386737581736712214586059366925008
      Line 381, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44046532397 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 44046532397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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