ADC_CTRL Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.060s	6.132ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.660s	842.558us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.160s	574.932us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.910m	52.606ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.560s	1.034ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.280s	543.346us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.160s	574.932us	20	20	100.00
		adc_ctrl_csr_aliasing	5.560s	1.034ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	17.736m	491.213ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.211m	487.781ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.254m	491.560ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.493m	499.123ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.525m	616.293ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.571m	571.599ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.993m	594.605ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	19.911m	546.447ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.040s	5.443ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.693m	43.130ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.570m	124.241ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	20.291m	389.162ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.880s	518.772us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.940s	517.140us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.810s	466.431us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.810s	466.431us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.660s	842.558us	5	5	100.00
		adc_ctrl_csr_rw	2.160s	574.932us	20	20	100.00
		adc_ctrl_csr_aliasing	5.560s	1.034ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.310s	5.127ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.660s	842.558us	5	5	100.00
		adc_ctrl_csr_rw	2.160s	574.932us	20	20	100.00
		adc_ctrl_csr_aliasing	5.560s	1.034ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.310s	5.127ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	9.590s	7.712ms	5	5	100.00
		adc_ctrl_tl_intg_err	19.450s	8.329ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	19.450s	8.329ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.864m	301.098ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.14

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 29.adc_ctrl_filters_both.80519515529519750096596645680355186510755226582280773099675912777852081493405
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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