ADC_CTRL Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.130s	5.983ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.750s	1.326ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.970s	489.377us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.315m	34.381ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.010s	1.120ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.260s	601.406us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.970s	489.377us	20	20	100.00
		adc_ctrl_csr_aliasing	6.010s	1.120ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.132m	488.958ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.605m	492.039ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.826m	497.395ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.406m	493.572ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	25.466m	652.327ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.718m	608.126ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.814m	568.001ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	22.079m	560.293ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.820s	5.167ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.746m	46.826ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.859m	128.390ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	40.545m	753.912ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	523.599us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.910s	515.119us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.440s	435.680us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.440s	435.680us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.750s	1.326ms	5	5	100.00
		adc_ctrl_csr_rw	1.970s	489.377us	20	20	100.00
		adc_ctrl_csr_aliasing	6.010s	1.120ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.690s	4.015ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.750s	1.326ms	5	5	100.00
		adc_ctrl_csr_rw	1.970s	489.377us	20	20	100.00
		adc_ctrl_csr_aliasing	6.010s	1.120ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	13.690s	4.015ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	20.120s	8.305ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.640s	8.824ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.640s	8.824ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	16.501m	707.516ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	16	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.07	96.67	100.00	100.00	98.83	98.33	91.56

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:116) [scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (* [*] vs * [*]) has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.adc_ctrl_stress_all_with_rand_reset.4712599005076116395466543318892568967710879618707328271698701497371443363481
      Line 408, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60651607690 ps: (adc_ctrl_scoreboard.sv:116) [uvm_test_top.env.scoreboard] Check failed m_interrupt == ((m_expected_intr_test || |m_expected_adc_intr_status) && intr_en) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 60651607690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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