ADC_CTRL Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.480s	5.847ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.410s	808.964us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.090s	548.981us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.720m	26.380ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.580s	1.057ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.180s	560.584us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.090s	548.981us	20	20	100.00
		adc_ctrl_csr_aliasing	5.580s	1.057ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.399m	507.373ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.416m	481.544ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.103m	490.894ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.661m	490.507ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	26.223m	655.670ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.488m	598.673ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.541m	600.000ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.147m	568.658ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.110s	5.327ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.750m	46.478ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.470m	122.010ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	25.447m	521.472ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.820s	532.296us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.870s	529.263us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.690s	593.832us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.690s	593.832us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.410s	808.964us	5	5	100.00
		adc_ctrl_csr_rw	2.090s	548.981us	20	20	100.00
		adc_ctrl_csr_aliasing	5.580s	1.057ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.440s	5.098ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.410s	808.964us	5	5	100.00
		adc_ctrl_csr_rw	2.090s	548.981us	20	20	100.00
		adc_ctrl_csr_aliasing	5.580s	1.057ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.440s	5.098ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	tl_intg_err	adc_ctrl_sec_cm	18.840s	7.562ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.030s	9.029ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.030s	9.029ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.610m	369.599ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			919	920	99.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.07	96.67	100.00	100.00	98.83	98.33	91.19

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_filters_both has 1 failures.

    • 21.adc_ctrl_filters_both.6284861646444611852291185910392306930719693668236782178102200442899950231933
      Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.01_10.49.01
• 2024.06.30_11.01.59
• 2024.06.29_09.26.22
• 2024.06.28_11.43.40
• 2024.06.27_11.00.44
• 2024.06.26_10.57.27