ADC_CTRL Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.460s	5.657ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.520s	1.131ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	483.115us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.622m	26.165ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.370s	1.062ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.670s	679.397us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	483.115us	20	20	100.00
		adc_ctrl_csr_aliasing	4.370s	1.062ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.147m	494.206ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.692m	494.354ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.251m	487.984ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.224m	497.801ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.638m	607.609ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.851m	598.246ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.038m	600.000ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.527m	631.334ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.920s	5.247ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.613m	40.826ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.622m	132.505ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	30.298m	575.865ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	1.840s	521.199us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.760s	492.801us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.190s	627.988us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.190s	627.988us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.520s	1.131ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	483.115us	20	20	100.00
		adc_ctrl_csr_aliasing	4.370s	1.062ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.810s	4.072ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.520s	1.131ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	483.115us	20	20	100.00
		adc_ctrl_csr_aliasing	4.370s	1.062ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.810s	4.072ms	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	tl_intg_err	adc_ctrl_sec_cm	10.490s	7.978ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.780s	8.656ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.780s	8.656ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	16.706m	1.328s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			918	920	99.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.07	96.67	100.00	100.00	98.83	98.33	91.17

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test adc_ctrl_filters_both has 2 failures.
  - 2.adc_ctrl_filters_both.111434827659538337276434310663026469327715996105805439206950971314566933824376
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.adc_ctrl_filters_both.27948996599449122987688292858043202664240243576028227185214314102755912369291
    Line 357, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ADC_CTRL Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9ae10fb42`