ADC_CTRL Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 14.920s 5.872ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.390s 718.497us 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 1.980s 526.213us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 51.630s 24.759ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.390s 952.928us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.260s 596.263us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 1.980s 526.213us 20 20 100.00
adc_ctrl_csr_aliasing 4.390s 952.928us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.616m 490.060ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.497m 490.952ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 19.514m 496.875ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.138m 500.829ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 22.269m 565.479ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 22.404m 574.641ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 20.812m 537.007ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 23.596m 589.390ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.380s 5.034ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.811m 45.165ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.018m 135.159ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 1.296h 2.204s 50 50 100.00
V2 alert_test adc_ctrl_alert_test 1.890s 527.009us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.780s 506.992us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.330s 407.309us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.330s 407.309us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.390s 718.497us 5 5 100.00
adc_ctrl_csr_rw 1.980s 526.213us 20 20 100.00
adc_ctrl_csr_aliasing 4.390s 952.928us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.060s 4.136ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.390s 718.497us 5 5 100.00
adc_ctrl_csr_rw 1.980s 526.213us 20 20 100.00
adc_ctrl_csr_aliasing 4.390s 952.928us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.060s 4.136ms 20 20 100.00
V2 TOTAL 740 740 100.00
V2S tl_intg_err adc_ctrl_sec_cm 16.670s 7.802ms 5 5 100.00
adc_ctrl_tl_intg_err 23.080s 8.154ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 23.080s 8.154ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 14.279m 756.022ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 919 920 99.89

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 16 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.22

Failure Buckets

Past Results